The present invention relates to a semiconductor device and, more particularly, to a technique effectively used for a semiconductor device having a transmission/reception circuit of the USB (Universal Serial Bus) 2.0 standard as an interface of a personal computer.
In a signal transmission/reception system, in the case of connecting the transmission side and the reception side via a transmission path, a termination resistor is connected to each of a transmission end and a reception end of the transmission path; and the resistance value of the termination resistors is set to a value according to the characteristic impedance of the transmission path to reduce the reflection effect at the transmission end and the reception end of a signal, thereby increasing the signal quality and the waveform quality. As the communication speed increases, it is desired to set the values of the termination resistors at the transmission and reception ends of signals more accurately and reduce the signal reflection effect. However, in the configuration of externally attaching the termination resistors at the transmission and reception ends of a transmission path, a transmission path of a certain distance exists from a transmission circuit to the mounting position of the transmission-side termination resistor and from the mounting position of the reception-side termination resistor to the reception circuit. Consequently, parasitic capacitance exists during transmission of a signal from the transmission circuit to the position of the transmission-side termination resistor and from the position of the reception-side termination resistor to the reception circuit, and there is a problem that the waveform quality deteriorates in the reception circuit. The configuration of externally attaching the termination resistors at the transmission and reception ends of the transmission path has a drawback of high manufacturing cost, and realization of integration of the termination resistors in an LSI is demanded.
Hitherto, to realize integration of termination resistors in a semiconductor LSI, for example, in the case of constructing the termination resistors only by built-in polysilicon resistive elements and diffusion resistive elements (which are manufactured simultaneously with a number of transistor elements and the like to be provided in the semiconductor LSI in the same manufacture process), the characteristics largely vary depending on the manufacture process, ambient temperature, application voltage, and the like, and desired termination resistor characteristics are not obtained. Japanese Unexamined Patent Application Publication No. 2005-64455 (semiconductor integrated circuit and signal transmission/reception system) proposes a system of a termination resistor having a circuit for adjusting gate bias of a MOS of a termination resistor or a MOS as a part of a termination resistor.
FIG. 12 shows a circuit corresponding to Japanese Unexamined Patent Application Publication No. 2005-64455. One end of a polysilicon resistive element R21 as a part of a termination resistor is connected to a power supply voltage terminal Vcc. The source node of a P-channel MOSFET QP11 as a part of the termination resistor is connected to the power supply voltage terminal Vcc. A control voltage generated by a gate bias voltage adjustment circuit is supplied to the gate of the P-channel MOSFET QP11. The gate bias voltage adjustment circuit adjusts the gate bias voltage of the P-channel MOSFET QP11 to adjust the resistance value of the P-channel MOSFET QP11. By controlling the resistance value of the P-channel MOSFET QP11, the value of the termination resistor constructed by the P-channel MOSFET QP11 and the resistive element R21 is controlled. A constant current source Iref passes a constant current Iref from the ground potential of the circuit via a parallel circuit of a polysilicon resistive element R20 and a P-channel MOSFET QP10 to the ground potential of the circuit. A reference voltage Vref is supplied to the inversion input (−) of a differential amplifier AMP and the voltage of the drain node of the P-channel MOSFET QP10 is fed back to the non-inversion input (+) of the differential amplifier AMP. The output node of the differential amplifier AMP is connected to the gate node of the P-channel MOSFET Q10 to feedback control the gate bias voltage of the P-channel MOSFET QP10 so that a voltage drop amount which occurs in the MOSFET QP10 and the resistive element R20 as a replica circuit becomes equal to the reference voltage Vref. Since the output node of the gate bias voltage adjustment circuit is also connected to the gate of the P-channel MOSFET QP11 as a part of the termination resistor, a combined resistance value between the power supply voltage terminal Vcc and a node n1 of an LSI pad to which a cable is connected also becomes the same expectation value as that set in the replica circuit. With such a configuration, the resistance value of the built-in termination resistor can be automatically adjusted to an expectation value.